From edf5f145013aa28ffbc7f19f874cd489a92f8449 Mon Sep 17 00:00:00 2001
From: rodri <rgl@antares-labs.eu>
Date: Sat, 5 Jun 2021 11:10:23 +0000
Subject: public release.

---
 asm/dht11/blink.s | 71 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 71 insertions(+)
 create mode 100644 asm/dht11/blink.s

(limited to 'asm/dht11/blink.s')

diff --git a/asm/dht11/blink.s b/asm/dht11/blink.s
new file mode 100644
index 0000000..5fe337f
--- /dev/null
+++ b/asm/dht11/blink.s
@@ -0,0 +1,71 @@
+.include "dat.h"
+
+vectors:
+	jmp start
+	jmp badirq	; IRQ0
+	jmp badirq	; IRQ1
+	jmp badirq	; PCINT0
+	jmp badirq	; PCINT1
+	jmp badirq	; PCINT2
+	jmp badirq	; Watchdog Timeout
+	jmp badirq	; Timer2 CompareA
+	jmp badirq	; Timer2 CompareB
+	jmp badirq	; Timer2 Overflow
+	jmp badirq	; Timer1 Capture
+	jmp badirq	; Timer1 CompareA
+	jmp badirq	; Timer1 CompareB
+	jmp badirq	; Timer1 Overflow
+	jmp badirq	; Timer0 CompareA
+	jmp badirq	; Timer0 CompareB
+	jmp badirq	; Timer0 Overflow
+	jmp badirq	; SPI Transfer Complete
+	jmp badirq	; USART RX Complete
+	jmp badirq	; USART UDR Empty
+	jmp badirq	; USART TX Complete
+	jmp badirq	; ADC Conversion Complete
+	jmp badirq	; EEPROM Ready
+	jmp badirq	; Analog Comparator
+	jmp badirq	; 2-wire Serial
+	jmp badirq	; SPM Ready
+
+start:
+	eor r1, r1
+	out SREG, r1
+	ldi r28, 0xff
+	ldi r29, 0x8
+	out SPL, r28
+	out SPH, r29
+	call main
+halt:
+	rjmp halt
+
+badirq:
+	jmp vectors
+
+.globl delayloop
+delayloop:
+	ldi r18, 82
+	ldi r19, 43
+	ldi r20, 0
+l1:
+	dec r20
+	brne l1
+	dec r19
+	brne l1
+	dec r18
+	brne l1
+	ret
+
+.globl main
+main:
+	ldi r16, 1<<DDRB4|1<<DDRB5
+	ldi r17, 0<<PORTB4|0<<PORTB5
+	out DDRB, r16
+	out PORTB, r17
+∞:
+	call delayloop
+	in r17, PORTB
+	com r17
+	;andi r17, 1<<PORTB4
+	out PORTB, r17
+	rjmp ∞
-- 
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