From 633a02454fd60da2e5a89fcc8ce82cb31044e0ac Mon Sep 17 00:00:00 2001
From: rodri <rgl@antares-labs.eu>
Date: Sat, 5 Jun 2021 12:01:24 +0000
Subject: public release.

---
 src/vga/vga.v | 44 ++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 44 insertions(+)
 create mode 100644 src/vga/vga.v

(limited to 'src/vga/vga.v')

diff --git a/src/vga/vga.v b/src/vga/vga.v
new file mode 100644
index 0000000..da9de58
--- /dev/null
+++ b/src/vga/vga.v
@@ -0,0 +1,44 @@
+module vga(
+	input wire clk,
+	output wire hsync,
+	output wire vsync,
+	output wire r,
+	output wire g,
+	output wire b
+);
+
+reg[9:0] hcnt;
+reg[9:0] vcnt;
+reg div;
+reg hpulse;
+reg vpulse;
+
+wire linedone = hcnt == (800-1);
+wire screendone = vcnt == (525-1);
+
+always @(posedge clk)
+	div <= div + 1;
+
+always @(posedge div) begin
+if(linedone) begin
+	hcnt <= 0;
+	vcnt <= vcnt + 1;
+end
+else
+	hcnt <= hcnt + 1;
+if(screendone)
+	vcnt <= 0;
+end
+
+always @(posedge div) begin
+	hpulse <= hcnt[9:4] == 0;
+	vpulse <= vcnt == 0;
+end
+
+assign hsync = ~hpulse;
+assign vsync = ~vpulse;
+assign r = vcnt[3] | hcnt & 1;
+assign g = vcnt[3] | hcnt & 1;
+assign b = vcnt[3] | hcnt & 1;
+
+endmodule
\ No newline at end of file
-- 
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