From 633a02454fd60da2e5a89fcc8ce82cb31044e0ac Mon Sep 17 00:00:00 2001 From: rodri Date: Sat, 5 Jun 2021 12:01:24 +0000 Subject: public release. --- src/blink/blink.qsf | 59 ++++++++++++++++++++++++++++++++++++++++++ src/blink/blink.v | 20 +++++++++++++++ src/blink2/blink.qsf | 56 ++++++++++++++++++++++++++++++++++++++++ src/blink2/blink.v | 18 +++++++++++++ src/pwm/pwm.qsf | 56 ++++++++++++++++++++++++++++++++++++++++ src/pwm/pwm.v | 15 +++++++++++ src/vga/vga.qsf | 72 ++++++++++++++++++++++++++++++++++++++++++++++++++++ src/vga/vga.v | 44 ++++++++++++++++++++++++++++++++ 8 files changed, 340 insertions(+) create mode 100644 src/blink/blink.qsf create mode 100644 src/blink/blink.v create mode 100644 src/blink2/blink.qsf create mode 100644 src/blink2/blink.v create mode 100644 src/pwm/pwm.qsf create mode 100644 src/pwm/pwm.v create mode 100644 src/vga/vga.qsf create mode 100644 src/vga/vga.v (limited to 'src') diff --git a/src/blink/blink.qsf b/src/blink/blink.qsf new file mode 100644 index 0000000..053582c --- /dev/null +++ b/src/blink/blink.qsf @@ -0,0 +1,59 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2017 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition +# Date created = 21:00:48 April 19, 2018 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# blink_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone IV E" +set_global_assignment -name DEVICE EP4CE6E22C8 +set_global_assignment -name TOP_LEVEL_ENTITY blink +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 17.1.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:00:48 APRIL 19, 2018" +set_global_assignment -name LAST_QUARTUS_VERSION "17.1.0 Lite Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 +set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V +set_global_assignment -name VERILOG_FILE blink.v +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_location_assignment PIN_23 -to clk +set_global_assignment -name CDF_FILE output_files/Chain4.cdf +set_location_assignment PIN_84 -to led1 +set_location_assignment PIN_85 -to led2 +set_location_assignment PIN_86 -to led3 +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/src/blink/blink.v b/src/blink/blink.v new file mode 100644 index 0000000..a8a0317 --- /dev/null +++ b/src/blink/blink.v @@ -0,0 +1,20 @@ +module blink( + input wire clk, + output wire led1, led2, led3 +); + +reg [31:0] cnt; + +initial begin + cnt <= 32'h00000000; +end + +always @(posedge clk) begin + cnt <= cnt + 1; +end + +assign led1 = cnt[24]; +assign led2 = cnt[23]; +assign led3 = cnt[22]; + +endmodule \ No newline at end of file diff --git a/src/blink2/blink.qsf b/src/blink2/blink.qsf new file mode 100644 index 0000000..67eaa80 --- /dev/null +++ b/src/blink2/blink.qsf @@ -0,0 +1,56 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2018 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition +# Date created = 10:56:13 July 08, 2018 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# blink_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone IV E" +set_global_assignment -name DEVICE EP4CE6E22C8 +set_global_assignment -name TOP_LEVEL_ENTITY blink +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.0.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:56:13 JULY 08, 2018" +set_global_assignment -name LAST_QUARTUS_VERSION "18.0.0 Lite Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 +set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V +set_global_assignment -name VERILOG_FILE blink.v +set_location_assignment PIN_23 -to clk +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_location_assignment PIN_84 -to led +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/src/blink2/blink.v b/src/blink2/blink.v new file mode 100644 index 0000000..8f0d4b8 --- /dev/null +++ b/src/blink2/blink.v @@ -0,0 +1,18 @@ +module blink( + input wire clk, + output wire led +); + +reg [31:0] cnt; + +initial begin + cnt <= 32'h00000000; +end + +always @(posedge clk) begin + cnt <= cnt + 1; +end + +assign led = cnt[26]; + +endmodule \ No newline at end of file diff --git a/src/pwm/pwm.qsf b/src/pwm/pwm.qsf new file mode 100644 index 0000000..d4f7e83 --- /dev/null +++ b/src/pwm/pwm.qsf @@ -0,0 +1,56 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2018 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition +# Date created = 00:20:02 July 15, 2018 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# pwm_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone IV E" +set_global_assignment -name DEVICE EP4CE6E22C8 +set_global_assignment -name TOP_LEVEL_ENTITY pwm +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.0.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:20:02 JULY 15, 2018" +set_global_assignment -name LAST_QUARTUS_VERSION "18.0.0 Lite Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 +set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V +set_global_assignment -name VERILOG_FILE pwm.v +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_location_assignment PIN_23 -to clk +set_location_assignment PIN_84 -to led +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/src/pwm/pwm.v b/src/pwm/pwm.v new file mode 100644 index 0000000..5d9e902 --- /dev/null +++ b/src/pwm/pwm.v @@ -0,0 +1,15 @@ +module pwm( + input wire clk, + output wire led +); + +reg[23:0] cnt; +always @(posedge clk) cnt = cnt + 1; + +wire[3:0] pwmin = cnt[23] ? cnt[23:19] : ~cnt[23:19]; +reg[4:0] pwm; + +always @(posedge clk) pwm <= pwm[3:0] + pwmin; + +assign led = pwm[4]; +endmodule diff --git a/src/vga/vga.qsf b/src/vga/vga.qsf new file mode 100644 index 0000000..6b41767 --- /dev/null +++ b/src/vga/vga.qsf @@ -0,0 +1,72 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2018 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition +# Date created = 11:28:26 July 15, 2018 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# vga_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone IV E" +set_global_assignment -name DEVICE EP4CE6E22C8 +set_global_assignment -name TOP_LEVEL_ENTITY vga +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.0.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:28:26 JULY 15, 2018" +set_global_assignment -name LAST_QUARTUS_VERSION "18.0.0 Lite Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 +set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_location_assignment PIN_23 -to clk +set_location_assignment PIN_101 -to hsync +set_location_assignment PIN_103 -to vsync +set_location_assignment PIN_106 -to r +set_location_assignment PIN_105 -to g +set_location_assignment PIN_104 -to b +set_global_assignment -name ENABLE_OCT_DONE OFF +set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF +set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name VERILOG_FILE vga.v +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/src/vga/vga.v b/src/vga/vga.v new file mode 100644 index 0000000..da9de58 --- /dev/null +++ b/src/vga/vga.v @@ -0,0 +1,44 @@ +module vga( + input wire clk, + output wire hsync, + output wire vsync, + output wire r, + output wire g, + output wire b +); + +reg[9:0] hcnt; +reg[9:0] vcnt; +reg div; +reg hpulse; +reg vpulse; + +wire linedone = hcnt == (800-1); +wire screendone = vcnt == (525-1); + +always @(posedge clk) + div <= div + 1; + +always @(posedge div) begin +if(linedone) begin + hcnt <= 0; + vcnt <= vcnt + 1; +end +else + hcnt <= hcnt + 1; +if(screendone) + vcnt <= 0; +end + +always @(posedge div) begin + hpulse <= hcnt[9:4] == 0; + vpulse <= vcnt == 0; +end + +assign hsync = ~hpulse; +assign vsync = ~vpulse; +assign r = vcnt[3] | hcnt & 1; +assign g = vcnt[3] | hcnt & 1; +assign b = vcnt[3] | hcnt & 1; + +endmodule \ No newline at end of file -- cgit v1.2.3