aboutsummaryrefslogtreecommitdiff
path: root/src/blink/blink.v
blob: a8a03176eb3231956b563851b8b170ff49403253 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
module blink(
	input wire clk,
	output wire led1, led2, led3
);

reg [31:0] cnt;

initial begin
	cnt <= 32'h00000000;
end

always @(posedge clk) begin
	cnt <= cnt + 1;
end

assign led1 = cnt[24];
assign led2 = cnt[23];
assign led3 = cnt[22];

endmodule