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| author | rodri <rgl@antares-labs.eu> | 2023-11-24 22:13:49 +0000 |
|---|---|---|
| committer | rodri <rgl@antares-labs.eu> | 2023-11-24 22:13:49 +0000 |
| commit | cc3307440e698d58843a5273519f4988c01937f1 (patch) | |
| tree | f166f1119e994d9f13b0f5cb85e4a0a44afce437 /dppd.s | |
| parent | 7cf4634e668730749aa8b7fa9ff16cf4234958fa (diff) | |
| download | amd64-simd-cc3307440e698d58843a5273519f4988c01937f1.tar.gz amd64-simd-cc3307440e698d58843a5273519f4988c01937f1.tar.bz2 amd64-simd-cc3307440e698d58843a5273519f4988c01937f1.zip | |
add more avx instructions and place VZEROUPPERs.
Diffstat (limited to 'dppd.s')
| -rw-r--r-- | dppd.s | 8 |
1 files changed, 8 insertions, 0 deletions
@@ -19,6 +19,7 @@ TEXT dppda(SB), 1, $0 VMOVUPD_128mr(8, rAX, rX0) /* VMOVUPD a+0(FP), X0 */ VMOVUPD_128mr(32, rAX, rX1) /* VMOVUPD b+24(FP), X1 */ VDPPD(rX1, rX0, rX0) /* VDPPD $0x31, X1, X0, X0 */ + VZEROUPPER RET TEXT dppd3(SB), 1, $0 @@ -42,6 +43,7 @@ TEXT dppd3a(SB), 1, $0 MOVSD a+16(FP), X1 MOVSD b+48(FP), X2 VFMADD231SD(rX1, rX2, rX0) + VZEROUPPER RET TEXT Pt2b(SB), 1, $0 @@ -89,9 +91,15 @@ TEXT xvec3(SB), 1, $0 MOVSD X0, 24(DI) RET +TEXT xvec3a(SB), 1, $0 + MOVQ SP, AX + ADDQ $8, AX + + TEXT fma(SB), 1, $0 MOVSD a+0(FP), X0 MOVSD b+8(FP), X1 MOVSD c+16(FP), X2 VFMADD231SD(rX1, rX2, rX0) + VZEROUPPER RET |