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authorrodri <rgl@antares-labs.eu>2021-06-05 11:10:23 +0000
committerrodri <rgl@antares-labs.eu>2021-06-05 11:10:23 +0000
commitedf5f145013aa28ffbc7f19f874cd489a92f8449 (patch)
tree05a7dfdae1b63a79bdfbb1fab84af35a51b5b99c /asm/dht11
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public release.HEADmaster
Diffstat (limited to 'asm/dht11')
-rwxr-xr-xasm/dht11/avrdasm2
-rw-r--r--asm/dht11/blink.s71
-rw-r--r--asm/dht11/dat.h25
-rw-r--r--asm/dht11/link.ld34
-rw-r--r--asm/dht11/makefile19
5 files changed, 151 insertions, 0 deletions
diff --git a/asm/dht11/avrdasm b/asm/dht11/avrdasm
new file mode 100755
index 0000000..ea0707b
--- /dev/null
+++ b/asm/dht11/avrdasm
@@ -0,0 +1,2 @@
+#!/bin/sh
+avr-objdump -D *.elf
diff --git a/asm/dht11/blink.s b/asm/dht11/blink.s
new file mode 100644
index 0000000..5fe337f
--- /dev/null
+++ b/asm/dht11/blink.s
@@ -0,0 +1,71 @@
+.include "dat.h"
+
+vectors:
+ jmp start
+ jmp badirq ; IRQ0
+ jmp badirq ; IRQ1
+ jmp badirq ; PCINT0
+ jmp badirq ; PCINT1
+ jmp badirq ; PCINT2
+ jmp badirq ; Watchdog Timeout
+ jmp badirq ; Timer2 CompareA
+ jmp badirq ; Timer2 CompareB
+ jmp badirq ; Timer2 Overflow
+ jmp badirq ; Timer1 Capture
+ jmp badirq ; Timer1 CompareA
+ jmp badirq ; Timer1 CompareB
+ jmp badirq ; Timer1 Overflow
+ jmp badirq ; Timer0 CompareA
+ jmp badirq ; Timer0 CompareB
+ jmp badirq ; Timer0 Overflow
+ jmp badirq ; SPI Transfer Complete
+ jmp badirq ; USART RX Complete
+ jmp badirq ; USART UDR Empty
+ jmp badirq ; USART TX Complete
+ jmp badirq ; ADC Conversion Complete
+ jmp badirq ; EEPROM Ready
+ jmp badirq ; Analog Comparator
+ jmp badirq ; 2-wire Serial
+ jmp badirq ; SPM Ready
+
+start:
+ eor r1, r1
+ out SREG, r1
+ ldi r28, 0xff
+ ldi r29, 0x8
+ out SPL, r28
+ out SPH, r29
+ call main
+halt:
+ rjmp halt
+
+badirq:
+ jmp vectors
+
+.globl delayloop
+delayloop:
+ ldi r18, 82
+ ldi r19, 43
+ ldi r20, 0
+l1:
+ dec r20
+ brne l1
+ dec r19
+ brne l1
+ dec r18
+ brne l1
+ ret
+
+.globl main
+main:
+ ldi r16, 1<<DDRB4|1<<DDRB5
+ ldi r17, 0<<PORTB4|0<<PORTB5
+ out DDRB, r16
+ out PORTB, r17
+∞:
+ call delayloop
+ in r17, PORTB
+ com r17
+ ;andi r17, 1<<PORTB4
+ out PORTB, r17
+ rjmp ∞
diff --git a/asm/dht11/dat.h b/asm/dht11/dat.h
new file mode 100644
index 0000000..5aed9cc
--- /dev/null
+++ b/asm/dht11/dat.h
@@ -0,0 +1,25 @@
+/* Data Registers */
+.equ PORTB, 0x05
+.equ PORTB0, 0
+.equ PORTB1, 1
+.equ PORTB2, 2
+.equ PORTB3, 3
+.equ PORTB4, 4
+.equ PORTB5, 5
+.equ PORTB6, 6
+.equ PORTB7, 7
+/* Data Direction Registers */
+.equ DDRB, 0x04
+.equ DDRB0, 0
+.equ DDRB1, 1
+.equ DDRB2, 2
+.equ DDRB3, 3
+.equ DDRB4, 4
+.equ DDRB5, 5
+.equ DDRB6, 6
+.equ DDRB7, 7
+/* Stack */
+.equ SPL, 0x3d
+.equ SPH, 0x3e
+/* Status Register */
+.equ SREG, 0x3f
diff --git a/asm/dht11/link.ld b/asm/dht11/link.ld
new file mode 100644
index 0000000..0e8fb64
--- /dev/null
+++ b/asm/dht11/link.ld
@@ -0,0 +1,34 @@
+OUTPUT_FORMAT("elf32-avr","elf32-avr","elf32-avr")
+OUTPUT_ARCH(avr:5)
+MEMORY
+{
+ text (rx) : ORIGIN = 0, LENGTH = 32K
+ data (rw!x) : ORIGIN = 0x800100, LENGTH = 2303
+ eeprom (rw!x) : ORIGIN = 0x800900, LENGTH = 1K
+}
+SECTIONS
+{
+ .text :
+ {
+ *(.vectors)
+ *(.text)
+ _etext = .;
+ } >text
+ .data :
+ {
+ *(.data)
+ . = ALIGN(2);
+ _edata = . ;
+ } >data AT>text
+ .bss ADDR(.data) + SIZEOF (.data) : AT (ADDR (.bss))
+ {
+ *(.bss)
+ *(COMMON)
+ . = ALIGN(2);
+ } >data
+ .eeprom :
+ {
+ *(.eeprom*)
+ } >eeprom
+ _end = .;
+}
diff --git a/asm/dht11/makefile b/asm/dht11/makefile
new file mode 100644
index 0000000..063bd39
--- /dev/null
+++ b/asm/dht11/makefile
@@ -0,0 +1,19 @@
+AS=avr-as
+LD=avr-ld
+LDSCRIPT=link.ld
+
+PORT=/dev/ttyACM0
+TARG=blink
+
+all: build
+
+build:
+ $(AS) -mmcu=atmega328p -c -o $(TARG).o $(TARG).s
+ $(LD) -T$(LDSCRIPT) -o $(TARG).elf $(TARG).o
+ avr-objcopy -j .text -j .data -O ihex $(TARG).elf $(TARG).hex
+
+burn:
+ avrdude -v -p atmega328p -c arduino -P $(PORT) -b 115200 -D -U flash:w:$(TARG).hex
+
+clean:
+ rm -f $(TARG).elf $(TARG).o $(TARG).hex