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| author | rodri <rgl@antares-labs.eu> | 2021-06-05 12:01:24 +0000 |
|---|---|---|
| committer | rodri <rgl@antares-labs.eu> | 2021-06-05 12:01:24 +0000 |
| commit | 633a02454fd60da2e5a89fcc8ce82cb31044e0ac (patch) | |
| tree | e9dd0abfef45ddaefdff01bcd586ceff9819332b /src/pwm | |
| download | fpgatoys-master.tar.gz fpgatoys-master.tar.bz2 fpgatoys-master.zip | |
Diffstat (limited to 'src/pwm')
| -rw-r--r-- | src/pwm/pwm.qsf | 56 | ||||
| -rw-r--r-- | src/pwm/pwm.v | 15 |
2 files changed, 71 insertions, 0 deletions
diff --git a/src/pwm/pwm.qsf b/src/pwm/pwm.qsf new file mode 100644 index 0000000..d4f7e83 --- /dev/null +++ b/src/pwm/pwm.qsf @@ -0,0 +1,56 @@ +# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2018 Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Intel Program License
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors. Please
+# refer to the applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition
+# Date created = 00:20:02 July 15, 2018
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+# pwm_assignment_defaults.qdf
+# If this file doesn't exist, see file:
+# assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus Prime software
+# and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone IV E"
+set_global_assignment -name DEVICE EP4CE6E22C8
+set_global_assignment -name TOP_LEVEL_ENTITY pwm
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.0.0
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:20:02 JULY 15, 2018"
+set_global_assignment -name LAST_QUARTUS_VERSION "18.0.0 Lite Edition"
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
+set_global_assignment -name VERILOG_FILE pwm.v
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_location_assignment PIN_23 -to clk
+set_location_assignment PIN_84 -to led
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file diff --git a/src/pwm/pwm.v b/src/pwm/pwm.v new file mode 100644 index 0000000..5d9e902 --- /dev/null +++ b/src/pwm/pwm.v @@ -0,0 +1,15 @@ +module pwm(
+ input wire clk,
+ output wire led
+);
+
+reg[23:0] cnt;
+always @(posedge clk) cnt = cnt + 1;
+
+wire[3:0] pwmin = cnt[23] ? cnt[23:19] : ~cnt[23:19];
+reg[4:0] pwm;
+
+always @(posedge clk) pwm <= pwm[3:0] + pwmin;
+
+assign led = pwm[4];
+endmodule
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