blob: 8f0d4b8656ed29580af786aa541c9400e48c51d1 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
|
module blink(
input wire clk,
output wire led
);
reg [31:0] cnt;
initial begin
cnt <= 32'h00000000;
end
always @(posedge clk) begin
cnt <= cnt + 1;
end
assign led = cnt[26];
endmodule
|
