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| author | rodri <rgl@antares-labs.eu> | 2021-06-05 12:01:24 +0000 |
|---|---|---|
| committer | rodri <rgl@antares-labs.eu> | 2021-06-05 12:01:24 +0000 |
| commit | 633a02454fd60da2e5a89fcc8ce82cb31044e0ac (patch) | |
| tree | e9dd0abfef45ddaefdff01bcd586ceff9819332b /src/blink/blink.v | |
| download | fpgatoys-master.tar.gz fpgatoys-master.tar.bz2 fpgatoys-master.zip | |
Diffstat (limited to 'src/blink/blink.v')
| -rw-r--r-- | src/blink/blink.v | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/src/blink/blink.v b/src/blink/blink.v new file mode 100644 index 0000000..a8a0317 --- /dev/null +++ b/src/blink/blink.v @@ -0,0 +1,20 @@ +module blink(
+ input wire clk,
+ output wire led1, led2, led3
+);
+
+reg [31:0] cnt;
+
+initial begin
+ cnt <= 32'h00000000;
+end
+
+always @(posedge clk) begin
+ cnt <= cnt + 1;
+end
+
+assign led1 = cnt[24];
+assign led2 = cnt[23];
+assign led3 = cnt[22];
+
+endmodule
\ No newline at end of file |