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| author | rodri <rgl@antares-labs.eu> | 2021-06-05 12:01:24 +0000 |
|---|---|---|
| committer | rodri <rgl@antares-labs.eu> | 2021-06-05 12:01:24 +0000 |
| commit | 633a02454fd60da2e5a89fcc8ce82cb31044e0ac (patch) | |
| tree | e9dd0abfef45ddaefdff01bcd586ceff9819332b /src/blink | |
| download | fpgatoys-633a02454fd60da2e5a89fcc8ce82cb31044e0ac.tar.gz fpgatoys-633a02454fd60da2e5a89fcc8ce82cb31044e0ac.tar.bz2 fpgatoys-633a02454fd60da2e5a89fcc8ce82cb31044e0ac.zip | |
Diffstat (limited to 'src/blink')
| -rw-r--r-- | src/blink/blink.qsf | 59 | ||||
| -rw-r--r-- | src/blink/blink.v | 20 |
2 files changed, 79 insertions, 0 deletions
diff --git a/src/blink/blink.qsf b/src/blink/blink.qsf new file mode 100644 index 0000000..053582c --- /dev/null +++ b/src/blink/blink.qsf @@ -0,0 +1,59 @@ +# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2017 Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Intel Program License
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors. Please
+# refer to the applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition
+# Date created = 21:00:48 April 19, 2018
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+# blink_assignment_defaults.qdf
+# If this file doesn't exist, see file:
+# assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus Prime software
+# and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone IV E"
+set_global_assignment -name DEVICE EP4CE6E22C8
+set_global_assignment -name TOP_LEVEL_ENTITY blink
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 17.1.0
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:00:48 APRIL 19, 2018"
+set_global_assignment -name LAST_QUARTUS_VERSION "17.1.0 Lite Edition"
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
+set_global_assignment -name VERILOG_FILE blink.v
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_location_assignment PIN_23 -to clk
+set_global_assignment -name CDF_FILE output_files/Chain4.cdf
+set_location_assignment PIN_84 -to led1
+set_location_assignment PIN_85 -to led2
+set_location_assignment PIN_86 -to led3
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file diff --git a/src/blink/blink.v b/src/blink/blink.v new file mode 100644 index 0000000..a8a0317 --- /dev/null +++ b/src/blink/blink.v @@ -0,0 +1,20 @@ +module blink(
+ input wire clk,
+ output wire led1, led2, led3
+);
+
+reg [31:0] cnt;
+
+initial begin
+ cnt <= 32'h00000000;
+end
+
+always @(posedge clk) begin
+ cnt <= cnt + 1;
+end
+
+assign led1 = cnt[24];
+assign led2 = cnt[23];
+assign led3 = cnt[22];
+
+endmodule
\ No newline at end of file |