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| author | rodri <rgl@antares-labs.eu> | 2021-06-05 12:01:24 +0000 |
|---|---|---|
| committer | rodri <rgl@antares-labs.eu> | 2021-06-05 12:01:24 +0000 |
| commit | 633a02454fd60da2e5a89fcc8ce82cb31044e0ac (patch) | |
| tree | e9dd0abfef45ddaefdff01bcd586ceff9819332b /src/pwm/pwm.v | |
| download | fpgatoys-master.tar.gz fpgatoys-master.tar.bz2 fpgatoys-master.zip | |
Diffstat (limited to 'src/pwm/pwm.v')
| -rw-r--r-- | src/pwm/pwm.v | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/src/pwm/pwm.v b/src/pwm/pwm.v new file mode 100644 index 0000000..5d9e902 --- /dev/null +++ b/src/pwm/pwm.v @@ -0,0 +1,15 @@ +module pwm(
+ input wire clk,
+ output wire led
+);
+
+reg[23:0] cnt;
+always @(posedge clk) cnt = cnt + 1;
+
+wire[3:0] pwmin = cnt[23] ? cnt[23:19] : ~cnt[23:19];
+reg[4:0] pwm;
+
+always @(posedge clk) pwm <= pwm[3:0] + pwmin;
+
+assign led = pwm[4];
+endmodule
|